Susuto

Latency and bottle necks seem to be a big part of the crysis challenge. A quicker solution would be to go wide. Going wide with the memory bus would give lower latency. Perhaps timing issues related to multi cores are part of it.. One solution that seems to follow the directional trend of Hypervisors would be a hardware chip to implement that and better manage cores and timing. Perhaps making the northbridge into something new and facilitating a new architecture..

Then perhapse 1ns memory will not be a requirement lol