Widening the bus does NOT reduce latency
Widening the bus does NOT reduce latency. The only solution for latency is to reduce the duration of read/write operations. Widening the bus is what we’ve been doing for the past few years because it’s been all we could do, and it lets us do more at a time, which–in some cases only–hides the effects of latency.
Do you even know what a hypervisor is? How about a memory controller, or what a northbridge even does?
And you certainly cannot reduce latency by widening the disconnect between CPU registers and main memory. Quite the contrary, that is why memory controllers and inter-core communication is being integrated directly into the CPU, and the GPU is exploring a closer relationship with the CPU.
1ns memory is the silver bullet we desperately need.